At today’s IEEE International Conference on Electronic Devices, IBM scientists demonstrated a series of breakthrough scientific research results that will greatly promote the development of smaller, faster, and more powerful processor chips.
IBM said that for more than 50 years, computer processors have been improving performance and reducing the size at an astonishing speed. Nowadays, they have completely relied on CMOS process technology. However, as Moore's Law approaches the limit, traditional methods will soon follow. To the end, there is no need to introduce new materials and circuit architecture. Unlike previous implementations in test rooms alone, IBM has now successfully applied new materials and new circuit architectures to 200-mm wafers, which is expected to provide a new technological foundation for computing, communications, and consumer electronics.
In the direction of carbon nanotubes, IBM took the first global carbon nano-transistor with a channel length (gate length) of less than 10 nm, which represents a major breakthrough in computing technology in the future, and is different from the previous on-state measurement. Performance performance, for the first time, IBM provides excellent off-state performance under extremely advanced processes, which is better than some current theoretical estimates.
IBM claims that the next decade will enter the post-10nm era, and for traditional silicon technology, it would be extremely difficult to evolve to such a size. Even if silicon transistors of this size can be made, it is difficult to compare performance with carbon nano-transistors.
In terms of graphene, IBM made the first CMOS compatible graphene integrated circuit (frequency multiplier) with a frequency of up to 5GHz, and it can work stably at a high temperature of 200°C. Although the details of its high temperature stability need further evaluation, it has opened the door to the use of graphene circuits in ultra-high temperature, high radiation environments.
Moreover, researchers have also used a new embedded gate structure to achieve a sufficiently high yield on 200-mm wafers.
New progress was made in the "Racerak Memory", which combines the features of magnetic mechanical hard disks and flash SSDs. For the first time, integration with CMOS technology was realized on 200-mm wafers in the 40-nm process. Sex development draws a successful conclusion, and below should consider how to be practical.
This time, IBM demonstrated how read and write functions can be implemented on an array of 256 levels of magnetic-level track. Based on this, the density and reliability of Racetrack storage can be further improved by using vertical magnetic track and 3D architecture. Ultimately, it is expected to access massive amounts of data in less than one billionth of a second.
IBM said that for more than 50 years, computer processors have been improving performance and reducing the size at an astonishing speed. Nowadays, they have completely relied on CMOS process technology. However, as Moore's Law approaches the limit, traditional methods will soon follow. To the end, there is no need to introduce new materials and circuit architecture. Unlike previous implementations in test rooms alone, IBM has now successfully applied new materials and new circuit architectures to 200-mm wafers, which is expected to provide a new technological foundation for computing, communications, and consumer electronics.
In the direction of carbon nanotubes, IBM took the first global carbon nano-transistor with a channel length (gate length) of less than 10 nm, which represents a major breakthrough in computing technology in the future, and is different from the previous on-state measurement. Performance performance, for the first time, IBM provides excellent off-state performance under extremely advanced processes, which is better than some current theoretical estimates.
IBM claims that the next decade will enter the post-10nm era, and for traditional silicon technology, it would be extremely difficult to evolve to such a size. Even if silicon transistors of this size can be made, it is difficult to compare performance with carbon nano-transistors.
In terms of graphene, IBM made the first CMOS compatible graphene integrated circuit (frequency multiplier) with a frequency of up to 5GHz, and it can work stably at a high temperature of 200°C. Although the details of its high temperature stability need further evaluation, it has opened the door to the use of graphene circuits in ultra-high temperature, high radiation environments.
Moreover, researchers have also used a new embedded gate structure to achieve a sufficiently high yield on 200-mm wafers.
New progress was made in the "Racerak Memory", which combines the features of magnetic mechanical hard disks and flash SSDs. For the first time, integration with CMOS technology was realized on 200-mm wafers in the 40-nm process. Sex development draws a successful conclusion, and below should consider how to be practical.
This time, IBM demonstrated how read and write functions can be implemented on an array of 256 levels of magnetic-level track. Based on this, the density and reliability of Racetrack storage can be further improved by using vertical magnetic track and 3D architecture. Ultimately, it is expected to access massive amounts of data in less than one billionth of a second.
Kaflon Measuring And Controlling Instruments Co., Ltd. , http://www.interwell-pen.com