An important consideration for embedded solutions is the high flexibility and scalability of processors, IP cores, and software components.
Your application may face a series of basic requirements in terms of price, performance, and functionality. When designing a product, you must find the best balance between these basic requirements. In addition, your needs may change during the product or design cycle in response to changes in the market. Therefore, you must develop your product with a highly flexible and scalable platform that allows you to make adjustments for each design at any time, without having to change platforms or partner companies.
This article describes the relationship between application requirements and network performance, discusses design considerations, and several design cases that meet the requirements.
Application requirements
According to the OSI standard, Ethernet is a physical layer interface. Among the various communication protocol standards used in the transmission and network layers, the TCP/IP communication protocol suite is the most commonly used standard, and as a result, it has become an existing industry standard for transmitting data on the network, especially in the aspect of embedded systems.
For simplicity, we use TCP load traffic as the main criteria for evaluating performance in later sections of this article. Table 1 lists the requirements of several sample applications and their TCP/IP load traffic.
| Application area | Traffic demand |
| Industrial Control / Monitoring | <1 Mbps |
| Security/monitoring | 10~50 Mbps |
| Broadcast quality video stream | 50~500 Mbps |
Table 1: Network Traffic Requirements for Various Applications
Xilinx Embedded Network Solutions
Xilinx Embedded Solutions provides all the necessary components for you to develop a wide variety of embedded networking systems. One of the key advantages of Xilinx embedded solutions is the high resiliency and scalability of processors, IP cores, and software components. You have the flexibility to start or shut down higher-level features in the processor, IP core, and software platform, and fine-tune many of the individual parameters until they can meet application requirements at the software level.
In addition, software functions with high or low performance can be identified by using performance testing tools, and appropriate hardware accelerators can be used to share the processing load.
The following describes three examples using the Xilinx Platform Studio (XPS) to design the Ethernet subsystem to meet typical application performance requirements. Each design contains a different system architecture, including processor configuration, Ethernet media access control component (MAC) IP configuration, and memory interface.
The example also describes the various TCP/IP software stacks that these hardware subsystems can be paired with. Since both the hardware building block and the software layer have built-in customization capabilities, you can gradually expand or reduce the effectiveness of these sample systems based on application requirements.
Ethernet "Lite" subsystem
The "Lite" network subsystem shown in Figure 1 is sufficient to support a simple web interface for remote monitoring or various control applications. In such applications, the TCP/IP performance requirements are rather low (less than 1 Mbps), so you can use the small TCP/IP stack LwIP (lightweight network communication protocol stack) instead of using a real-time operating system (RTOS) ).
You can use the simple polling mode in the Ethernet "Lite" IP to build this system without interruption. You can also combine complete software, including a simple application layer, and then integrate it all into the local memory in the Xilinx FPGA. In this basic network subsystem, you can add other necessary I/O interfaces like RS-232 UART and GPIO (as shown in Figure 1).
Typical Fast Ethernet (10/100) Subsystem
You can change the minimum size system described above to achieve higher TCP/IP processing traffic (10>50 Mbps) and move to more common 10/100 Ethernet solutions as shown in Figure 2. Key changes include:
Adding a direct memory access (DMA) engine to the Ethernet MAC becomes an interrupt-driven component.
Add external memory to the system and add the cache to the processor.
Use a more sophisticated TCP/IP stack, such as Clinux in the Linux operating system.
You can use the Base System Builder wizard in XPS to easily develop the MicroBlaze design.
High-performance Gigabit Ethernet subsystem
For applications that need to support TCP/IP traffic above 100 Mbps, you can effectively use the hard IP of the three-mode Ethernet media access control components that are pre-built on several specific Xilinx FPGA family components (shown in Figure 3). . For higher-level applications requiring more than 500 Mbps of traffic, you must use many advanced DMA technologies such as distributed/collected DMA (SGDMA), such as Data Reconfiguration Engine (DRE) and Check-Code Processing Offload (CSO). FPGA hardware accelerators.
There are several high-performance PowerPC 405 processors built on Xilinx FPGAs, built-in 16-Kb instructions, and data capture at 450MHz operating frequency to support a variety of software platforms, including Linux, VxWorks, Integrity, and QNX. Allows you to develop a variety of systems using a variety of high-performance web interfaces.
Figure 4 compares the three types of network subsystem TCP/IP load traffic previously discussed. The Y-axis flow data is a logarithmic value to facilitate the comparison of performance values ​​that have a large gap.
Factors affecting TCP performance
Many factors affect the performance of TCP, including hardware and software. In a system, these related factors affect TCP traffic:
Processor
Frequency Frequency: The TCP/IP communication protocol stack usually first copies the user buffer load traffic to the stack-controlled buffer and then to the FIFO component of the Ethernet MAC. When working in software, some memory copy jobs use processor cycles. The processor also involves checking the TCP check code, including reading the entire packet's data from memory. Faster processors with faster memory can perform two jobs in less time and keep up with the speed of data transfer.
Features: The TCP/IP communication protocol stack involves accessing packet headers and payload traffic. In a header processing operation, a typical access operation includes reading a specific information bit in the header, causing a displacement; and each packet must be processed by addition and multiplication operations one by one. In a configurable processor such as a MicroBlaze soft processor, you must enable instructions to perform shift registers or multiplication operations in order to achieve higher performance.
Caching: Once a packet is copied from the Ethernet media access control component to memory, it is sent to the various functional layers of the TCP/IP communication protocol stack for processing. At this point, the packet processing code in the TCP/IP stack enters the execution phase. Putting program code and packets into cache can greatly increase the efficiency of the processor and increase the bandwidth of Ethernet.
2. Memory
Memory access time and delay have a great impact on system performance. A typical TCP/IP communication protocol stack application cannot cope with local memory programs and data as part of external memory. The time it takes to access data and instructions has a significant impact on performance. Memory factor is usually directly related to cache capacity. Increasing the cache capacity of instructions and data will help reduce the transfer latency and access time of external memory.
3. Ethernet media access control components
The peripheral components of the Ethernet media access control component built on the FPGA are quite similar in terms of operating mode (without DMA and SGDMA relative issues), packet FIFO depth, DRE and CSO support capabilities, and giant frame support capabilities. Provides considerable flexibility. However, the space consumed by each of the above options by the MAC component will be able to offload processor functions, thereby improving performance.
4. TCP/IP communication protocol stack
Optimized and flexible TCP/IP stack construction is an important factor to improve system performance. Including TCP/IP stack functions such as support for CSO in hardware, APIs for no replication jobs (data does not have to be copied from the application to the stack buffer), and configurable stack options to match application requirements all contribute to improved system performance .
5. Information size
The size of information (application data) is another factor that affects performance. The smaller the information, the higher the proportion of resources consumed by TCP/IP communication protocol headers (such as TCP, IP, and Ethernet headers) and the amount of data traffic that can be obtained.
in conclusion
There is a big gap between the requirements of network efficiency for various embedded applications, and it will change with the evolution of the product life cycle. To design the ideal product to meet a wide variety of evolving needs, you need a highly flexible and scalable solution tailored to your application needs.
Xilinx's embedded solutions developed for PowerPC and MicroBlaze processors are equipped with a complete lineup of tools and customizable IP to help you develop scalable network subsystems and address a wide variety of application needs. Plan for proper performance.
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