1 McBSP (MulTIchannel Buffered Serial Port) serial port uses the multi-frame (MulTI-Frame) communication interrupt processing in DMA
In an actual communication application, after a burst, the program must be prepared for the next burst. Therefore, the serial port DMA multi-frame mode is generally used, but there are some problems to be discussed when the serial port transmits data by DMA. First, the DMA transfer synchronization event should set the transmission event of the McBSP, that is, XEVT, so that another byte is automatically prepared after one byte transfer (the READY rising edge of McBSP triggers the DMA transfer). When an interrupt occurs, it means that a block has been transmitted. At this time, the DMA enable is automatically turned off, and the READY of McBSP will remain high. But when the next burst transfer directly enables DMA, it can't start the transfer (I believe there will be many problems I have encountered). This is because the READY rising edge required for the McBSP trigger to start is not generated. The solution is to close the transmission of McBSP in the interrupt program, make READY="0", then send the enable DMA in the program, and then open the transmission of McBSP. If you open the DMA after sending the McBSP, it will not work. Since the READY of McBSP has changed from 0 to 1, it is no longer possible to generate a READY rising edge.
2 The difference between closing DMA and closing McBSP
In the field of communication, in order to make full use of the on-chip peripheral resources of the DSP, DMA is often used to put data from the serial port or data to be sent into a buffer and then process. For DMA, an interrupt is generated as long as its pointer to the data buffer points to where the interrupt should occur. But at this time, the last data only enters the McBSP and is not actually sent out. Therefore, only the DMA can be turned off and the McBSP cannot be closed in the interrupt program at the end of the transfer. Because there is still a word in the DXR of the register of McBSP at this time.
3 Key timing of McBSP serial port configuration
Mainly the configuration of the register SPCR2: configure the other serial port control registers while keeping the RRST, XRST, and FRST bits to zero. Wait for at least 2 CLKR/T clocks to ensure synchronization within the DSP.
(1) You can load data to DXR or enable DMA.
(2) Enable GRST (GRST = 1) (if the DSP needs to generate the sampling clock internally).
(3) Enable RRST or XRST. Note that only this bit changes in the SPCR.
(4) Enable FRST (FRST = 1) (if the DSP needs to generate frame synchronization internally).
(5) After waiting for 2 R/T CLK clock cycles, the receiving or transmitting end will be valid.
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