With the rapid development of computer technology, electronic information technology is more and more quickly spread to applications in all walks of life. The traditional way of collecting logistics information is to check the ticket through the staff, and then input the data on the ticket into the computer. This process is time-consuming and labor-intensive, and may cause the existence of various erroneous data due to various human errors, which affects the reliability of the collected information. The automatic identification technology uses a computer for automatic identification, which increases the flexibility and accuracy of input, makes people get rid of complicated statistical identification work, and greatly improves the work efficiency of logistics information collection. At present, RFID applications promoted by large supermarkets such as Wal-Mart and Metro have brought benefits to the retail industry including lower labor costs, improved visibility of commodities, lower losses caused by out-of-stock commodities, and fewer thefts. The applicable process includes: real-time statistics of sales data of goods, replenishment, anti-theft, etc. This article uses RFID technology, using FPGA chip and NRF905 to build a wireless communication system, successfully realized wireless transmission and reception of data.
1 System design
1.1 Introduction to RFID
RFID (Radio Frequency IdenTIficaTIon, radio frequency identification technology) is to use radio waves to read / write recording media. The distance of radio frequency identification can reach tens of centimeters to several meters, and according to the way of reading / writing, thousands of bytes of information can be input, and at the same time, it has extremely high confidentiality. Application areas of RFID technology: material tracking, delivery vehicles and shelves
It is especially suitable for occasions that require non-contact data collection and exchange, such as identification, and occasions that require frequent changes in data content. For example, Hong Kong's automatic vehicle identification system is easy to drive, and the main technology used is radio frequency technology. Radio frequency technology has also been widely used in the automatic management of identification of other items.
As shown in Figure 1, it is the entire framework of the wireless system, which is composed of the control module, SPI module and antenna module. Among them, the configuration of the SPI module is completed by the control module through the Wishbone bus, and the configuration, mode conversion, and data transmission and reception of the antenna module are all completed by the control module through the SPI bus. Each part will be explained below.
1.2 Antenna module (NRF905 transceiver module)
1.2.1 Introduction to NRF905
NRF905 is a monolithic RF transmitter chip launched by Nordic in Norway. The operating voltage is 1.9 to 3.6 V. It is packaged in a 32-pin QFN and works on three ISM channels of 433/868 / 915MHz. It can automatically complete the work of processing the header and CRC (Cyclic Redundancy Code Check), the Manchester encoding / decoding can be automatically completed by the on-chip hardware, and the SPI interface is used to communicate with the microcontroller, the configuration is convenient, the power consumption is low, -10 dBm The output power is only 11 mA when transmitting, and 12.5 mA when in receiving mode.
NRF905 has ShockBurst receiving and ShockBurst sending two working modes; power-down and SPI programming and Standby and SPI programming two power saving modes. The characteristic of its ShoekBurst working mode is that the preamble and CRC are automatically generated, and can be programmed and configured through the SPI interface. The working mode of NRF905 is set up by the settings of TRX_CE, TX_EN, PWR_UP, see Table 1.
1.2.2 NRF905 configuration and working process
All configuration of nRF905 is carried out through SPI interface. The SPI interface consists of 5 registers, and one SPI instruction is used to decide what operation to perform. The SPI interface is only active in power-down mode and Standby "mode.
The five registers of the SPI interface are:
(1) Status register: The register contains data ready DR and address matching AM status.
(2) RF configuration register: The register contains configuration information such as the frequency and output power of the transceiver.
(3) Send address: The register contains the address of the target device, and the byte length is set by the configuration register.
(4) Send valid data: the register contains the valid Shock Burst packet data sent, and the byte length is set by the configuration register.
(5) Receive valid data: The register contains the valid ShockBurst packet data received, and the byte length is set by the configuration register. The valid data in the register is indicated by the data ready DR.
ShoekBurst technology enables nRF905 to provide high-speed data transmission without the need for high-speed controllers for data processing or clock coverage. By putting high-speed signal processing related to the RF protocol into the chip, nRF905 provides an SPI interface to the application controller, and the rate is determined by the interface speed set by the microcontroller itself. nRF905 reduces the average current consumption in the application by reducing the speed of the digital application part when the RF is connected at the maximum rate through the ShockBurst working mode. In the ShockBurst RX (receive) mode, the address matching AM and data ready DR signals inform the controller that a valid address and data packet have been received separately. In ShockBurst TX (transmit) mode, nRF905 automatically generates preamble and CRC check code, data
The ready DR signal informs the controller that the data transmission has been completed.
1.3 SPI module
1.3.1 Introduction to SPI bus
SPI (Serial Parallel Bus) is a synchronous serial peripheral interface proposed by Motorola, allowing the CPU to communicate with various peripheral interface devices in a serial manner. It uses 4 lines: serial clock line (SCK), master input / slave output line (MISO), master output / slave input line (MOSI), active low signal line (SS). In this way, only 3 to 4 data lines and control lines are needed to expand various I / 0 devices with SPI interface.
The data in SPI bus mode is transmitted in bytes (multiple bytes can be transmitted in one transmission), each byte is 8 bits, and each command or data block is byte aligned (an integer of 8 clocks) Times). The data is transmitted bit by bit, with the high bit in the front and the position in the back. For full-duplex communication, the data transmission speed is generally faster than the I2C bus, and the speed can reach several megabits per second. The SPI interface works in a master-slave manner. This mode usually has a master device and one or more slave devices. In the wireless communication system designed in this paper, the SPI bus interface module implemented by FPGA is the master, and the SPI module of NRF905 is the slave.
Selection of SPI timing mode:
The SPI interface has 4 different data transmission timings, taking the combination of CPOL and CPHL. CPOL is used to determine the level of the SCK clock signal when it is idle; CPOL = O, the idle level is low, and when CPOL = 1, the idle level is high. CPHA is used to determine the sampling time, CPHA = 0, sampling at the first clock edge of each cycle; CPHA = 1, sampling at the second clock edge of each cycle.
Figure 2 is the timing diagram of the SPI interface of NRF905, so the SPI working mode designed in this article is under the timing of CPOL = O, CPHA = O.
1.3.2 SPI hardware design
Figure 3 is the structural diagram of the SPI module in this article's wireless communication system. The SPI in this system is mainly composed of a clock generation module, SPI register set, and SPI function configuration module, and is connected to the controller through the Wishbone bus. The specific design is as follows:
Clock generation module: Because the SPI module is implemented based on FPGA, and the clock provided outside the FPGA is faster (50 MHz or 100 MHz), it is not suitable for communication with the SPI interface of NRF905
(1 Hz ～ 10 MHz), so frequency division is needed to slow down the clock. But as for the frequency division, it is done by the SPI function configuration module. Secondly, because the SPI protocol indicates that the data can be triggered on the rising or falling edge, it is also necessary to identify the rising or falling edge of the clock (also called the edge capture program). This function is also completed by this module.
SPI register module: This module implements a 128-bit register group consisting of 16 8-bit registers, which means that it can send and receive 8-128 serial data at a time through the SPI interface. The specific operation is completed by the SPI function configuration module.
SPI function configuration module: This module is equivalent to an SPI controller. The configuration of its registers determines the frequency division of the clock, the number of data bits sent and received, the data transfer of the rising or falling edge of the clock, and the configuration of these registers is Completed by the control module. The configuration registers are briefly described below.
First introduce the control register:
Control register bit 0 go: whether to start sending.
The first bit rx_negedge of the control register: whether the received data is a falling edge or a rising edge.
The second bit of the control register tx_negedge: whether the transmitted data is a falling edge or a rising edge.
The 3rd to 9th char_len of the control register: the number of bits of transmitted data (since SPI is full-duplex, so this is actually the number of bits of received data).
The tenth lsb of the control register: whether to send from the high bit or status.
The 11th bit of the control register ie: whether to send an interrupt signal after reading and writing.
The 12th bit of the control register ass: whether to automatically generate chip select signal.
Divider register: spi_divider_sel.
Status register: spi_ctrl_sel.
Data register O: spi_tx_sel [0].
Data register 1: spi_tx_sel [1].
Data register 2: spi_tx_sel [2].
Data register 3: spi_tx_sel [3].
Chip select signal register: spi_ss_sel.
1.4 Control module
For the control module, its implementation method is to use the finite state machine based on Verilog language to achieve, equivalent to one by one instruction to control the SPI module to receive and send data. The control module is divided into three independent parts: the receiving control module, the sending control module, and the NRF905 configuration module. Among them, the receiving and sending control modules respectively contain the state of configuring the SPI. The design of the receiving control module is explained below. Figure 4 shows the transition diagram of the state machine synthesized by Debussy.
There are many states designed to complete wireless communication, which are more complicated, so only a brief description of the more important states is made. Idle idle state, complete the initialization of the port to clear the register; config_div state, divide the clock (define sclk); configwb_in state, define the number of transmitted data and whether to send or receive on the rising edge or falling edge, wb_inl, wb_in2, wb_in3 , Wb_in4, these four states are the number to write to the SPI configuration through the Wishbone bus interface (each state corresponds to a register); configspi_out state, start to transfer data; done state, chip select high data transfer is completed; readeonfigreg_prel state, set Set the number of data bits to be sent; readconfigreg (read register control word bits) status, read command word for SPI configuration via Wishbone bus interface; readconfigreg_out status, set send / receive data bits; alldone status, chip select high to complete configuration data reading Fetching process.
The design takes into account the correctness of the configuration process, so the state of reading the configuration data of the register is deliberately set. Ehangemode is the receiving state. When the reception is completed (DR = 1), it enters the eh-angmodee state and reads the received data. . Then return to the readeonfigreg_prel state and wait for new transmission data.
2 System verification
The design was finally verified at the board level. The FPGA development board and the NRF905 PCB board constituted this verification system. The FPGA chip adopts Xilinx's XC2V1000. The comprehensive tool used is Synplify. The tool used to view the waveforms in pre-simulation and post-simulation is Modelsim. The layout and wiring tool and download tool used are iMPACT integrated with ISE 10.1, while the board level The tool used to test the waveform is Chipseope.
Before downloading, sufficient functional simulation was performed on this design, and the SPI slave was written in Verilog to simulate the SPI interface of NRF905 to communicate with the SPI host to ensure that the preset functions could be completed.
Download is to download the configuration file to a specific FPGA chip. In this article, the JTAG download method is used. The download tool uses the integrated tool iMPACT of Xilinx ISE. The purpose of pin binding before downloading is to be able to constrain the input / output ports of the design to the appropriate pins of the FPGA chip, so as to facilitate its analysis and debugging and connect with external I / O. The following is the relevant content in the corresponding pin constraint file in this design.
After the download is complete, connect the FPGA development board to the NRF905 PCB according to the pin binding. Figure 5 shows the PCB connection diagram for wireless transceiver.
This is just one of the ends, here assumed to be the receiving end, then there is also the same interconnecting PCB board as the sending end. The PCB on the right is FPGA used to implement SPI module and control module. The small PCB board with an inverted embossed shape on the upper left side is the NRF905, and the PCB board on the left serves to connect the FPGA and the NRF905, and provides power to the NRF905.
After the system is established, the next step is the final board-level verification. Fig. 6 is a waveform diagram obtained by Chipscope. mosi and miso are the signals on the SPI bus of the sender and receiver respectively. It can be seen from the figure that the data is basically consistent, which shows that the wireless communication system designed by FPGA to control NRF905 can work normally.
3 Conclusion
This paper implements a wireless communication system controlled by FPGA with NRF905. Through the establishment and simulation test of the system and board-level verification, it proves that the wireless communication system can work normally, and the communication distance of the wireless system can reach 100 m, which basically completes the wireless system communication. The requirements fully explain the practicability of the design system.
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