AD6655: Mixed-Signal IF Receiver (with data sheet)

Photocoupler

Summary:

The AD6655 is a mixed-signal IF receiver with dual-channel, 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADC and a wideband digital downconverter (DDC). Designed to provide solutions for low cost, small size, and versatile communications applications.

This dual ADC core features a multi-stage, differential pipeline architecture with integrated output error correction logic. Each ADC features a wide bandwidth, differential sample-and-hold analog input amplifier that supports user-selectable input ranges. An integrated voltage reference simplifies the design. The duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The ADC data output is internally connected directly to the receiver's digital down converter (DDC) to simplify layout and reduce interconnect parasitics. The digital receiver has two channels for flexible processing. Each receive channel has four cascaded signal processing stages: 32-bit frequency converter (CNC oscillator, NCO), half-band decimation filter, fixed-point FIR filter, and fADC/8 fixed-frequency NC expansion

In addition to the receiver DDC, the AD6655 has several features that simplify the automatic gain control (AGC) function in the system receiver. The fast detection feature enables fast overrange detection by outputting four-bit input level information with very short delays.

In addition, with the ADC's four fast detection bits, the programmable threshold detector monitors the power of the incoming signal with very short delays. If the input signal level exceeds the programmable threshold, the coarse threshold high limit indicator goes high. Because of the short delay of this threshold indicator, the user can quickly reduce the system gain to avoid overrange conditions.

The second function associated with AGC is the signal monitor. This module allows the user to monitor the composite amplitude of the incoming signal, which helps to set the gain to optimize the overall dynamic range of the system.

Once digital processing is complete, the data can be routed directly to two external 14-bit output ports that can be set to 1.8 V to 3.3 V CMOS or 1.8 V LVDS. CMOS data can also be output at double data rate using only port A, in an interleaved configuration.

The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of ?40°C to +85°C.

The product focuses on an integrated dual, 14-bit, 150 MSPS ADC.
Integrated wideband decimation filter and 32-bit complex-signal NCO.
Fast overrange detection and signal monitor with serial output.
The patented differential input maintains excellent signal-to-noise ratio (SNR) performance at input frequencies up to 450 MHz.
Flexible output modes including stand-alone CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
The SYNC input can synchronize multiple devices.
The 3-bit SPI port is used for register programming and register readback.

Multi-channel digital receiver (3G) for the application of communication radio systems
TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation system smart antenna system general software radio broadband data application

The AD6655 product data sheet can be found in the PDF document (click to download)