Not all portable systems are as simple as the system shown in Figure 1 (see the second part of this series). Figure 3 shows a typical block diagram of a wearable electronic device. Design complexity is further enhanced by the large number of functional blocks and subsystems.
Figure 3: High-level block diagram of the watch
A logical approach is to split the entire system into different subsystems and analyze the power consumption of each subsystem. This also helps simplify the design of the power domain for low power consumption.
The power consumption of the display and touch controller sections is primarily dependent on the backlight driver and the display itself. Most designs use a timer-based timeout mode for the display. In general, after a fixed time T1, the backlight will drop to a 50% duty cycle, and after a time T2, the display will turn off completely. At this time, even the touch controller can be turned off or enters the power-off mode, depending on the usage scenario. In this way, the designer can plot the current curve of this function block to get the typical current.
Wireless controllers, such as Bluetooth-oriented controllers, are typically low power. This controller can switch between high and low power modes in a certain way. The typical values ​​in the wireless controller datasheet are the closest power estimation estimates we can get without analyzing the system performance. However, we have to remember to consider the duty cycle of the device between different power modes.
The sensor current is primarily dependent on the excitation current and the power consumption of the analog front end (AFE). Cypress's PSoC 4 and other devices have built-in analog functions such as ADCs and other AFE components, which allows designers to dynamically power down different function blocks with firmware commands. This level of control and fine granularity further enhances the efficiency of low power designs.
For complex designs involving multiple controllers and multiple operating modes, care must be taken to accommodate different controllable power domains during power supply circuit design. In this way, a single controller on a standby power domain can effectively control other domains. This architecture may be costly, but it can maintain very low power consumption.
After each subsection is clarified, the power consumption of each subsection can be optimized in the following ways:
1. Turn off the regulator to turn off the entire subsection
2. Power off unused peripherals
3. Reduce average power consumption using the microcontroller's low power mode
The most efficient way to achieve low power consumption is to turn off the regulator used to power the stator. If a particular subsection does not need long-term availability and its functionality is not time critical, then its regulator itself can be controlled by the host controller. The sensor is a good example of a subsystem that can be turned off when the system is not running. The only leakage current that will be consumed will be the current of the regulator.
If you cannot power down the entire subsection, consider the various peripherals and components of the subsection. For example, in the sensor section, there may be some sensors that need to continue to measure and some that do not. Suppose there is a thermistor that measures temperature, an accelerometer, and an IR sensor. The accelerometer needs to check frequently for activity, and the rest of the system needs to wake up accordingly. In contrast, temperature sensors and IR sensors do not need to work most of the time. Let us talk about the excitation of the thermistor (see Figure 4). In this example, the current passes through the thermistor and reference resistor, whether or not the measurement is taken.
Figure 4: Typical thermistor excitation circuit
Now, if the thermistor circuit is modified as shown in Figure 5, current consumption can be avoided when the sensor is not being sampled.
Figure 5: Thermistor excitation for low power consumption
In this example, the pin is configured for a strong output mode (CMOS inverter). The pin is driven low to measure the sensor output. This causes the thermistor to be connected to Vss through the NMOS transistor. The only additional resistance to consider is the on-resistance of the NMOS transistor, which is essentially very low. When the sensor output is not required to be measured, the pin is driven high. This causes the thermistor to be connected to Vdd, thereby achieving zero current on the sensor circuit.
Since the accelerometer does not need to be sampled at any time, the ADC and other analog components (such as op amps or reference generators in the analog signal chain) can be powered down when no signal is needed.
There are many other ways to reduce power consumption when implementing this circuit with SoC, which we will describe below. Imagine the system shown in Figure 3. The LCD controller can enter hibernation mode and the host processor can wake up when it senses an I2C command. With PSoC 4 implemented in the circuit, power consumption can be as low as 20 nA.
Similarly, if the sensor subsection is implemented in a low power mode and all components will be turned off, the MCU can wake up with a comparator interrupt in the presence of motion. The accelerometer output can be connected to the comparator to ensure that the device wakes up as soon as motion is active and triggers the host processor's events.
For systems built on SoC, other techniques can be used to reduce average power consumption. For example, the clocks of all peripherals can be set to the slowest clock frequency. Since dynamic power is proportional to the switching frequency, this can save power. As another example, the clock frequency of an ADC in an SoC should typically be proportional to the desired sample rate. If the sampling rate set by the ADC is higher than the actual system requirements, it will cause unnecessary battery load.
There are other system level techniques that can be used to reduce overall power consumption. For example, the device output can support a lower conversion rate to reduce radiation. However, a lower slew rate will cause the FET's pin driver stage to consume more current because both PMOS and NMOS will turn on longer. Depending on the amount of radiation allowed by the system, the conversion rate of the pin can be adjusted.
The device we choose can simplify the implementation of low-power systems if it offers multiple power modes and achieves higher levels of integration and better control of the SoC's power state. Depending on the application, we can effectively use different power modes to ensure a lower average current. Although higher clock frequencies result in higher power consumption, the CPU's temporary high frequency operation can then return the device to sleep more quickly, which actually helps achieve lower average power consumption. Developers should consider the overall system and avoid leak current paths as much as possible.
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