The clock device design employs an I2C programmable fractional phase-locked loop (PLL) to meet high-performance timing requirements. This approach ensures a frequency with zero PPM (parts per million) of synthesis error. High-performance clock ICs typically offer multiple clock outputs to drive various subsystems within applications like printers, scanners, and routers—such as processors, FPGAs, data converters, and more. Complex systems like these often require dynamic updates to the reference clock frequency to accommodate different protocols, including PCIe and Ethernet.
The clock IC functions as an I2C slave, requiring the host controller to configure its internal PLL logic. This control logic can be written directly to the microcontroller. Acting as an I2C master, the microcontroller configures the internal volatile memory of the clock IC and controls the PLL. Consequently, the system clock frequency can be dynamically updated through the onboard MCU-IC combination. Programmable microcontrollers provide the necessary control logic for high-performance clock ICs, resulting in a more compact design and reduced material costs by minimizing the number of onboard ICs and traces.
The theory of operation involves a basic PLL architecture for high-performance clock devices. This design uses a scaling factor to synthesize the clock output frequency. The final output frequency is calculated using the formula:
\[ f_{\text{out}} = \frac{f_{\text{ref}} \times \text{DIV}_N}{\text{DIV}_R \times \text{DIV}_O} \]
Where:
- \( f_{\text{ref}} \) is the input reference crystal frequency (typically between 8 MHz and 48 MHz).
- \( \text{DIV}_R \) represents the division factor of the input frequency reference (a prescaler).
- \( \text{DIV}_N \) is the fractional-N factor.
- \( \text{DIV}_O \) is the post-divide factor before output.
Figure 1 illustrates the PLL block diagram for a simplified high-performance clock. The orange blocks represent programmable parameters, and the equations using these parameters are adjustable. These parameters can be programmed at the factory and written to the non-volatile memory of the clock device. The device contains both volatile and non-volatile memory, with the non-volatile memory pre-configured at the factory. Upon powering up, the contents of the non-volatile memory are copied to the volatile memory, allowing the PLL to produce the desired default clock output.
One key feature of the clock IC is its ability to be reprogrammed during runtime via the I2C interface. This allows users to make immediate changes by altering the volatile memory contents. Users can implement these instant programming changes using the appropriate I2C instructions from the host controller.
The non-volatile memory can also store multiple predefined user configurations. Using the Frequency Select (FS) function, users can choose between these configurations. The FS-pin is a CMOS input pin that selects a configuration file stored in non-volatile memory based on an N-bit external CMOS signal. This selected configuration is copied to volatile memory, and the PLL outputs a different signal accordingly.
Microcontrollers play a crucial role in controlling the clock IC's PLL. As shown in Figure 2, the microcontroller communicates with the clock IC over the I2C interface. The clock IC's internal PLL block generates a tuning voltage (Vtune) as a fixed DC voltage, which varies depending on the frequency band. The PLL module takes the local oscillator frequency as input and amplifies it using an internal preamplifier. Additionally, the prescaler reduces the input frequency and passes it to the phase comparator.
Figure 3 illustrates how the microcontroller sends data to the programmable divider via I2C. The divider also receives input from a reference oscillator, such as a 4 MHz crystal oscillator. The phase comparator compares the local oscillator frequency (e.g., 87.15 MHz) with the reference oscillator frequency (after being divided by the programmable divider). If they match, the phase comparator generates the Vtune tuning voltage. Any mismatch between the local oscillator frequency and the microcontroller frequency data results in no tuning voltage or output.
With the help of a microcontroller, the PLL forms a closed loop by tuning the local oscillator frequency and producing a tuning voltage. The tuning voltage adjusts from the lower frequency channel to the higher frequency channel. The microcontroller can fine-tune the step size by modifying the prescaler and programmable divider values.
\[ \text{Step Size} = \left( \frac{\text{Local Oscillator Frequency}}{\text{Prescaler}} \right) \times \left( \frac{\text{Programmable Divider}}{\text{Reference Oscillator}} \right) \]
Table 1 shows some configuration examples.
In-system programming via the I2C interface enables rapid and efficient system design iterations. The programming data sequence can be transferred to the clock device via the SCL and SDA pins. The microcontroller (acting as the master) programs the sequence of operations, interacting with the slave clock at runtime using commands and data.
For instance, consider a system where the clock signal must be a multiple of the sample rate. This clock frequency needs to switch flexibly between 155.52 MHz and 156.25 MHz. The microcontroller master can adjust the PLL configuration in volatile memory to meet these two frequency requirements.
High-performance clock devices support multiple user profiles with personalized configurations. The FS-pin offers two timing specifications: fast switching and slow switching. Fast switching applies to output ON/OFF, crossover value changes, and output MUX settings. Slow switching is useful for changing PLL parameters, including turning the PLL ON/OFF. While fast switching leads to quicker output changes, slow switching is more gradual. Both types ensure error-free output transitions. Figure 4 demonstrates the timing relationship between FS and the output clock.
External reset functionality allows the clock IC to enter a low-power mode when triggered. During this mode, the output and I2C bus signals are in a high-impedance (HI-Z) state until the reset is canceled and initialization completes. The external reset clears the volatile memory contents and copies the configuration from non-volatile memory to volatile memory. This feature is useful for reinitializing applications on any system.
Voltage Controlled Crystal Oscillator (VCXO) functionality modifies the PLL frequency, ensuring the frequency pull is independent of crystal characteristics, temperature, voltage, or device process. VCXO modulation is linear and precise. A clock reference can also be used, and the built-in analog module of the microcontroller ensures accurate control logic to six decimal places.
Using programmable microcontrollers simplifies the design of high-performance clock ICs, reducing the need for additional onboard ICs and traces. This makes the overall system design more compact and cost-effective. Microcontrollers come equipped with powerful IDE tools to accelerate application development. Integrated Programmable System-on-Chip (PSoC) devices further simplify the design process, helping reduce overall product costs.
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