S3C2410 pin
The S3C2410 LCD Controller is used to transmit video data and generate necessary control signals, such as VFRAME, VLINE, VCLK, VM, etc. In addition to the control signal, S3C2410 also has a port VD [23 z O] to output video data, as shown in Figure 1. The pins to be used are described as follows: VCLK-pixel clock signal; VD [23: O]-LCD pixel output port; VM / VDEN / TP-LCD driver AC bias signal (STN) / data enable Signal (TFT) / SEC TFT source driver data load pulse signal.
Figure 1 S3C2410 LCD controller external pin diagram
The LCD controller consists of REGBANK, LCDCDMA, VIDPRCS, TIMEGEN and LPC3600 (see Figure 2).
REGBANK has 17 programmable register sets and 256 × 16 palette memory, used to set the LCD controller. LCDCDMA is a dedicated DMA that automatically transfers video data from the frame memory to the LCD controller. With this special DMA, video data can be displayed on the screen without CPU intervention. VIDPRCS accepts the video data from LCDCDMA and changes it to the appropriate data format via VDF23: O] and sends it to the LCD driver, such as 4/8 single scan or 4 double scan display mode. TIMEGEN consists of programmable logic to support the different requirements of the interface timing and rate of different LCD drivers. TIMEGEN generates VFRAME, VLINE, VCLK, VM signals, etc.
The data flow is described as follows: FIFO memory is located in LCDCDMA. When the FIFO is empty or partially empty, LCDCDMA requires data from the frame memory based on the burst transmission mode to store the image data to be displayed. This frame memory is a buffer created by the LCD controller in RAM. When this transfer request is received by the bus arbiter in the storage controller, 4 words will be successfully transferred from the system memory to the internal FIFO. The total size of the FIFO is 28 words, of which the lower FIFOL is 12 words and the upper FIFOH is 16 words. S3C241O has two FIFOs to support dual scan display mode. In single scan mode, only one FIFO (FIFOH) is used.
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