This diagram represents the core components of the H.264 codec IP designed by Atria Logic.
The AL-H264E-4KI422-HW encoder is a hardware-based solution that delivers high-quality, low-latency H.264 (AVC) encoding for UHD Hi422 video. It works seamlessly with the AL-H264D-4KI422-HW decoder, ensuring efficient and accurate decoding of the encoded stream.
Key features of the IP include:
- Comprehensive modular design for user customization and scalability
- Support for intraframe H.264 and Hi422 5.1 encoding and decoding
- Integrated HDMI 2.0 receive and transmit subsystem
- Support for 8-bit and 10-bit video streams
- Compatibility with RGB and YUV 4:2:2/4:4:4 color formats
- Ultra-low latency of approximately 0.3 seconds
- Support for both variable bit rate (VBR) and constant bit rate (CBR)
- Excellent video quality with SSIM above 0.99% or PSNR over 50dB
- Video pre/post-processing capabilities, including color space conversion, scaling, and subsampling
- Support for Gbps Ethernet output
To evaluate our UHD encoding and decoding IP cores for 4K@60fps performance, we needed a flexible and powerful platform. After careful consideration, we selected the Xilinx ZC706 evaluation kit based on the Zynq Z-7045 SoC for the following reasons:
The board includes a ready-made FMC expansion card that provides a 4K HDMI video interface (TB-FMC-HDMI 4K 2.0 version).
The Zynq Z-7045 SoC offers rich programmable logic resources, making it ideal for implementing the encoder and decoder IP while meeting strict timing requirements.
It also features a dual-core ARM Cortex-A9 processor, enabling us to develop custom application software and GUI interfaces for enhanced user experience.
The H.264 encoder supports Hi422 format and 5.1 standard (3840x2160p30) intraframe encoding, along with 10-bit video support, which prevents any loss of color or brightness during video transmission. The YUV 4:2:2 format ensures better color accuracy, especially for red tones, leading to sharper images—critical for medical imaging applications.
This diagram illustrates the internal structure of the Atria Logic UHD H.264 Encoder IP module.
Intraframe coding allows the encoder to maintain minimal frame delay, and its macroblock pipeline architecture further reduces latency to about 0.3 milliseconds. This design supports eight pixels per clock cycle, enabling real-time 4K@60fps encoding.
The H.264 encoder uses only 78% of the Zynq Z-7045’s programmable logic and DSP resources, and 55% of available RAM, leaving ample space for other necessary functions.
The H.264 decoder also supports Hi422 format and 5.1 standard intraframe encoding, along with 10-bit video and YUV 4:2:2 compatibility. Its pipelined architecture helps achieve low latency, making it ideal for real-time applications.
This image shows the internal structure of the Atria Logic UHD H.264 Decoder IP module.
Low latency is crucial for closed-loop systems involving human or machine interaction. When the AL-H264E-4KI422-HW encoder and AL-H264D-4KI422-HW decoder are connected via an IP network, the total glass-to-glass delay is approximately 0.6 milliseconds (excluding transmission time), equivalent to about two frames.
The decoder implementation uses 68% of the Zynq Z-7045’s programmable logic, 35% of DSP resources, and 45% of RAM, leaving room for additional circuitry.
The HDMI subsystem consists of two main modules: the HDMI TX and RX subsystems. These modules handle the conversion between serial and parallel data streams, as shown below:
The GTX module handles the physical layer interface, converting serial HDMI data into parallel data using the Zynq SoC’s high-speed GT transceiver.
The HDMI TX subsystem includes a transmit module, AXI Video conversion, video timing control, and an optional HDCP module. It supports 8, 10, and 12-bit data encoding and transmits video and audio AXI streams to the HDMI TX module.
The HDMI RX subsystem processes incoming video and audio signals, converting them into AXI Stream data and managing timing and control through various interfaces.
The HDCP module is optional and not included in the default IP core configuration.
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