Recommended use of dvteclipse software

Below is a brief introduction to some of the key features of the software.

First, Automatic Completion

When you type part of a word and press Ctrl + Space, a dialog box appears with suggestions for completion. You can select the desired option to automatically complete the text.

DVT also supports abbreviation completion. For example, if you type u_t_p and press Ctrl + Space, it will automatically expand to uvm_table_printer.

Second, Class Type Hierarchy

To view the type hierarchy of a class, right-click on the class name and select Show > Type Hierarchy, or use the F4 shortcut.

This feature shows the inheritance chain of a class. For instance, the ubus_example_base_test class inherits from uvm_test, which in turn inherits from uvm_component, and finally from uvm_void. Additionally, ubus_example_base_test has three subclasses: test_2m_4s, test_r8_w8_r4_w4, and test_read_modify_write.

Third, Macro Expansion

This feature stands out as one of the most useful. Unlike other tools like VCS or IRUN, DVT allows you to expand macros directly, so you can see the code after macro expansion. This helps in understanding what the macro actually does.

For example, in UVM, we often use the `uvm_component_utils macro to register classes. However, after expansion, it's not always clear what the macro does. By right-clicking on the macro name and selecting Macros > Expand All Levels, you can view the expanded code.

You can now see the code after expansion, with all macro parameters replaced. This makes it easier to understand how the macro works and what it contributes to the class structure.

Fourth, Statement and File Navigation

If you want to jump to the declaration of a function or the source file of an included header, simply hover over the symbol, hold down the Ctrl key, and select the appropriate option from the dialog box.

Fifth, Display UVM Structure

When working with UVM environments, we usually use the print_topology() function to print the structure. However, DVT allows you to view the UVM hierarchy directly within the tool.

Right-click on the top-level test and choose Show > Verification Hierarchy.

In the Verification Hierarchy panel, you can see the full structure of the UVM environment when ubus_example_base_test is the top level.

Sixth, Generate UML Diagrams for Classes

To generate a UML diagram for a class, right-click on the class name and select Show > Diagram.

This will display a UML diagram that visually represents the class structure, making it easier to understand relationships and components.

Seventh, Automatically Generate UVM Fields

If you have variables that you want to include in the UVM field automation mechanism, you can use the UVM Field Editor.

Right-click in the code area and choose Source > UVM Field Editor.

A dialog box will appear where you can select the variable on the left and set its properties on the right.

Click OK to generate the corresponding code automatically.

Eighth, Editor Selection

For Linux users who prefer editors like Vi or Emacs, DVT supports these as well. In the upper-right corner, there’s a drop-down menu that lets you choose your preferred editor.

Ninth, Code Formatting

If the code formatting is messy, you can easily fix it. Right-click in the code area and select Source > Format Source.

After formatting, the code becomes more readable and structured.

Tenth, Lint Functionality

DVT includes a linting feature that helps analyze your code for compliance with SystemVerilog and UVM standards. Right-click on the project and select Lint with > SystemVerilog UVM Compliance Rules.

A dialog box appears, allowing you to customize the linting rules and review any issues found.

Eleventh, Project Build

Once your code has been modified, you can rebuild the project by right-clicking on it and selecting Project > Rebuild.

DVT offers many powerful features that make working with SystemVerilog and UVM more efficient. It’s highly recommended to explore the tool further to discover more of its capabilities.